Processing repeater for TDMA communication system

ABSTRACT

The present invention relates to a processing repeater for use in a TDMA communication system which is capable of providing the individual data terminals with synchronization error measurements and other control data. In the particular embodiment disclosed, the processing repeater is also capable of receiving a narrowband coarse synchronization signal from an inactive data terminal in response to an interrogation command, thereby permitting rapid initial synchronization to be achieved. The disclosed processing repeater is also capable of controlling the demand assignment process for the allocation; of time slots in response to either narrowband or wideband call requests from inactive or active data terminals respectively.

Schlosser et al.

[4 1 Apr. 22, 1975 PROCESSING REPEATER FOR TDMA COMMUNICATION SYSTEM Inventors: Leslie R. Sehlosser, Los Angeles;

James B. Reeves, Reseda. both of Calif.

Assignee: Hughes Aircrait Company, Culver City. Calif.

Filed: Nov. 24, 1972 Appl. No.: 309.371

[52] U.S. Cl. l79/l5 BS; 325/4 [5 l] Int. Cl. H04j 3/06 [58] Field of Search 179/15 BS; 325/4; l78/69.5 R

[56] Relerences Cited UNITED STATES PATENTS 3.639.838 2/1972 Kuhn 325/4 3.730.998 5/1973 Schmidt 179/15 BS 3.742.498 6/1973 Dunn 179/15 BS Primary E.\'aminerRa1ph D. Blakcslee Attorney, Agent, or Firm-John M. May; W. H. MacAllister. Jr.

[57] ABSTRACT The present invention relates to a processing repeater for use in a TDMA communication system which is capable of providing the individual data terminals with synchronization error measurements and other control data. In the particular embodiment disclosed, the pro cessing repeater is also capable of receiving a narrowband coarse synchronization signal from an inactive data terminal in response to an interrogation command. thereby permitting rapid initial synchronization to be achieved. The disclosed processing repeater is also capable of controlling the demand assignment process for the allocation; of time slots in response to either narrowband or wideband call requests from inactive or active data terminals respectively.

6 Claims, 57 Drawing Figures auribur linl PHENYEB MR 2 21975 SHEET OlUF 34 1 MI Framn 4-H Dommlidt m :ynchroniznr dmndulnor roaivnr r r r 550- 53M 52M Bittimlng 5'0 O 59' Ducodcr m 5'" Timinq and control unit Tqminrl DmIColnuyncmblu (A: controlur mum) Colrlnyncsignll II-D i 540- Coda O r 5m 560 (530* 520.1 590; I I

a o Rm Uplink 4/2-Phli0 Uplink 5 L m format-hr 7 modulator mm FIG. 3.

Tlmu slot mode COARSE SYNC SIGNAL Terminal lddns Subscriber addm F I G. I 7. MEMORY DATA WORD FORMAT SZTDMACOMMUNICATION SYSTEM FATUHEE APR 2 2 i975 3.879.581 SHEET DH [IF 34 420 Receive Transmit antenna 400 when antenna burst demod/bit 450 synchronizer Uplink communication 4-phase Downlink J receiver P mod transmitter 410 21mm I burst F I G- 4 S TDMA SPACECRAFT REPEATER Leedinv 141 {.F. signal 33 from u I' k receiver} m "gnal sync detector Trellmg 1 edge 1 143 Coarse L Timing (clock) gg 730 Democzuleted fmm Transition detector Trensition 742 enable dgmodulatq Transmon detector F IG. 7 COARSE SYNC DECTECTOR Reset (from initialization mode control) Terminal active (from RAM no.3)

WB cell r we call request mum a 'fi not detected d y? T s From burst code control assignment ck t) synchronizer WB on" request detected Time slot 4 assignment 4800 From mined programmer All circuits busy I L accepted Load I Terminal Terminal Buffer address (to register RAM no. 1 and RAM no. 1) RAM no. 3 and L48) programmer) F G. 4 8 WIDEBAND CALL REQUEST DETECTION CONTROL PATENTEDAPRZZIBIS 3,879,581

sum or or 34 Wait for coarsa sync 800 signal loading odp Loading cdqa 741 Wait for transition 82o Transition 742 Ganorato ooana sync 83 datoctad pulu Wait for initialization indication Wlit f0! coarse sync simai trialing adga Trailing odga 744 Powar turn-on or command 8 COARSE SYNC DETECTION Transmit tormination pattam and write availabio in all calls in RAM no. 1

t I 300m:

Rout controllers and ID counter control Timing INITIALIZATION CONTROL PATENIEUarazzms 3.879.581

saw cm 3:.-

Timing (to communication processor circuits) Time decoder 67 2 MHz Frame u clock MHZ pu bit ag ast rate clock 67.2 MHZ generator timing mum (168) (800) lnterrogate interrogate coda Data syn envelope 960 Uplmk bit clock 4. Upllnk data (from 4- l demod) bit timing Unique word detection (from burst code sync) 910 Cell termination word occurrence 4 detector g 930 Non- Occurrence NOTE: occurrence 5. 970 Means parallel data transfer Call termination detected Terminal active I (from RAM no. 3) t (Pall Rm ermlnation detection J 920 00mm l crement Timino (clock) n Start Of tlme'siot F'G. 9 CALLTERMINATlON DETECTOR A APR 2l975 P TENTH] 2 SHE Us 311 3 879 581 Wait for fimn slot Ditlctnd Wait ior uniqua word Beat wont counw Timing 2% Wait for call urminution word pumrn Non-occurrence Increment mm Oocurnncl Start0f Time Slot Stir! of timu slot FIG. CALL TERMINATION DETECTION PATENTEU APR 22 i975 Synchronization SHEET 103F134 FIG. ll

DATA FORMATTER and control field data (from synchronizer 1101 and control fiald programmer) Sl m raglster 1110 1 7 1 1 Read Downlink I19. 1 clock E311 om '1" coda steering igai Envelop logic no. o t t 1 1 Di ital data (to Uplink bit Rad Downlink multi ploxar downlink clock 2 modulator) (from 1 103 sun: I 4-phase demod) Write 3 no. 2 a 112 i 22'': Road Dovjnlink no. 3 cl 1 1 1 Parallel-in serial-out shift register Dovmlink clock G 1130 Termination Read no. 1 pattern (H.Wl Read no. 2- Read no. 3

Initialization mode (from initialization T control) D 1150 7 I. K 4 A Road no. 1

Do rk Do rk -Floodno.2

wn 1n wn m clock channel 4 and 4 generator timing Rad In 3 A Load sync and control J L field 1140 Downlink 1160 bit rate clock 52.4 mHz A Minor frame Wm. 1 ync (from n0. 2 uplink tima 1 A Write no. 3 slot timing) jl'ima I101 Minor tlockklLricivm J Write 12:: mm B 1 t 212 1 Frame sync 2" number PATENTEU E 3.879.581

SHEET llJF 34 lnputdata TsaooU T31 U T521 Ll T54 L] L] T86 T87 [I- 1 Time slot period 2.5 microseconds Write 1 WriteZ "L l' i l l l m3 l i l 'i Reed 4 I I M 1 l l 'l l' l M2 w Read3 J Output data cmsaI cHsooIs&c|=| CH1 I can I CH3| c|-|4| cus lcl-ls NOTES:

1. 1 Minor frame 32 time slots DATA FOHMATTER TIMING 1mm sootimflbfl I- Time slot period $235; FL H H Fl II fl W H Fl 11 n n J Read/write n n Fl Load R Write 1 Write 2 Termination sequence Write 3 Clock F IG. TIME SLOT STATUS MEMORY CONTROL TIMING PAifiNiiinirnzzisrs 3.879.581

Initialization mod. (from initialization mods control) Minor from. sync cod! lhlrdwirldl Minor um F J\ number From Rood no. 4 data form DOVII'IIiI'Ik clock Load sync and control field r r W d r:::( 2333? ml From comml'ldfld O -m to (it. controllers terminal W formthrl addresses Commands Digital (hardwired) multiploxor From 322222? sand RAM C:: no 2 L -144o L 4 1430 o o o film All circuits "My busy acccpmd iorlood Priority Ti 7 Prowlrnmor Called Terminal mock 3 timing T8 0 comrol fim W a x controller] 1410 J I ll 1420 I O O Inurroptc Y 0 From 0 oomrollors All circuit busy roldy F G. l 4 SYNCHRONIZATION AND CONTROL FIELD PROGRAMMER PATENTEBiPRnms 3.879.581

interrogate commend clrcufis busy lnitiel cell com commend Fine sync Coarse maintenance sync em transmission 11 l trensmisslon Suscriber 2 Reedy 2 initial address for time slot transmission load assignment (celled terminal) Fine sync error transmission Supplemental subscriber call command 9 gddm transmission Ceiling terminal time slot assignment FIG. SYNCHRONlZATION AND CONTROL FIELD PROGRAMMER PATENTEB Z Terminate -t SHEET ISUF 34 J Wait for aad Start-of-TS Write U t1 Write 1 Wait for delay Write Load data registers Terminate 0 t F'G. TIME SLOT STATUS MEMORY PAiENiEuli'iizziais 3.879.581

saw 15 SF 34 Initialization mode (from initialization control) Start of T.S.

Write-call 5 termination Call termination detected 1) (from cell termination ----y c n detector) termination Write/decrement control (to RAM no. 3) Wrlte accepted (from RAM no. 1)

2 F I 4 6 CALL TERMINATION CONTROL initialization Power turn-on o Reset (to all Initialization Initialization can, RM

command I (from 8/6 t 300 commend M decorder) countdms Frame rate clock C (from uplink time J slot timing) F i 2 0 INITIALIZATIONCONTROL Coarse sync control ready (from coarse signal m ID and control) 1 Start Of time slot I (to Coarse sync detected Coarse error (from coarse sync detector) measure control Reset Timing (clock) 1 l Measure J g g enable Measure clock Course sync accepted mum i 3 g {y L- 2910 c o g- 3 Buffer Coarse error measurement 0 Buffer ([0 Time slot number 0 I: I: Subtractor programmfl') (from time slot counter)[ 0 G 2920 800 (H.W.)

F I COAHSE SYNC ERROR MEASUREMENT COUNTER PATENTEDAPR22I975 Reset A/ Wait Start initial cells Wait for concurrence of new call, not initial fine sync, terminal inactive and terminal address equal to terminal address counter Store terminal address in buffer register, store time slot number in time slot buffer storage memory and set initial fine sync bit I iwms Delay Ail terminals not celled INTERROGATQ AND INITIAL CALL CONTROL Reset identification sync counter Minimum link delay PATENTED APRZ 2 i913 SHEET 1 8 OF 34 Time slot Called term number Buffer (from time RAM 2 MW me slot slot counter) number nm m l Reed Clk

Addreee eelection w/n Write i Read m time slot m time slot (from called (from coarse "mm" W interrogate coarse sync address counter identification and in interrogate eontrol) and and call control) F l G. 2 4 TIME SLOT BUFFER MEMORY Not Terminal zero active I detector inactive K 3700 4} Terminal address (from: RAM no. 1) g Terminal E: l RAM no. 3 3;: 5 2 counter w n call request detector) l l g g R/W L 3710 Write/increment (from fine sync measurement control) llrlIrsita/incrament (from increment assignment control) RAM no 3 Write/increment (from Deerement supplemental call control) Write/demment (from cell 3720 termination detector control) Timing lnitializetion mode (from initialization mode oontrol) TERMINAL STATUS MEMORY 

1. In a time division multiple access communication system having a plurality of data terminals, each terminal capable of transmitting an uplink burst of data within an assigned time slot, and all capable of receiving an essentially continuous stream of downlink data, a processing repeater for receiving a burst transmission from one of said data terminals and for transmitting it within a frame of said stream of data to another of said terminals, said processing repeater comprising: means for generating a common timing standard; means for receiving and demodulating uplink transmission bursts within assigned time slots; means for detecting a predetermined unique word within each of said bursts; means for measuring the synchronization error of the detected unique word within an uplink transmission burst from a particular one of said plurality of data terminals with respect to said common timing standard; and means for encoding the measured synchronization error as digital data within a synchronization and control field provided as part of said stream of data, whereby said particular data terminal is provided an indication of the timing correction required to maintain synchronization between the data bursts transmitted by said terminal and said common timing standard generated by said processing repeater.
 1. In a time division multiple access communication system having a plurality of data terminals, each terminal capable of transmitting an uplink burst of data within an assigned time slot, and all capable of receiving an essentially continuous stream of downlink data, a processing repeater for receiving a burst transmission from one of said data terminals and for transmitting it within a frame of said stream of data to another of said terminals, said processing repeater comprising: means for generating a common timing standard; means for receiving and demodulating uplink transmission bursts within assigned time slots; means for detecting a predetermined unique word within each of said bursts; means for measuring the synchronization error of the detected unique word within an uplink transmission burst from a particular one of said plurality of data terminals with respect to said common timing standard; and means for encoding the measured synchronization error as digital data within a synchronization and control field provided as part of said stream of data, whereby said particular data terminal is provided an indication of the timing correction required to maintain synchronization between the data bursts transmitted by said terminal and said common timing standard generated by said processing repeater.
 2. The processing relay of claim 1 further comprising means for selecting which of successive ones of said data terminals is to have its uplink transmission burst synchronization error measured by said measuring means, whereby uplink transmission interference between said successive data terminals actively transmitting bursts of data may be avoided.
 3. The processing relay of claim 2 further comprising: means for assigning a second time slot to a data terminal already transmitting data bursts in a first assigned time slot; and means for encoding a digital representation of the second assigned time slot as part of said stream of downlink data.
 4. The processing relay of claim 2 further comprising: means for assigning an initial time slot to a data terminal not already transmitting data bursts in an assigned time slot; means for encoding a digital representation of the initial time slot assignment as part of said stream of downlink data.
 5. In a communications satellite adapted for use in a time division multiple access communications system, the combination comprising: means for receiving and demodulating wideband uplink data bursts; means for establishing synchronization between various ones of said data bursts originating from different data terminals such that they are received by said satellite sequentially in a non-overlapping fashion separated by a guard time; means for buffering and encoding said data bursts as part of a downlink stream of free from any guard time intervals having a narrower bandwidth than that of said data bursts; and means for transmitting said downlink stream of data. 